A power-on reset (POR) circuit, as that term is used herein, is a circuit which produces a delayed output signal in response to the initial application of power to the circuit or upon momentary interruption of the power. Such circuits may be used, for example, for placing counters, registers, memories, or other circuits in a desired initial condition.
Selection of a power-on reset circuit for a particular application may involve one or more of the following criteria: static and dynamic response, operating voltage range, steady state power dissipation, and ease of implementation in integrated circuit form. The static and dynamic response should be such that the circuit operation is essentially independent of the supply voltage rise time. The operating voltage range should be such that the reset circuit does not require more voltage than the device with which it is to be used which otherwise would limit the operating range of the utilization device. The steady state power dissipation should be minimal and, ideally, zero. Finally, the circuit should not require a great deal of silicon area when implemented as an integrated circuit.
A problem often encountered in Metal Oxide Semiconductor (MOS) circuits is a sensitivity to variations in transistor threshold voltages. Typically, a switching point for determining when to begin the generation of the output signal is based on the threshold voltages of several MOS transistors. Variations, then, in the transistor threshold voltages due to processing variations will cause undesired changes in the switching point and hence the timing of the output signal, or worse no output signal.
Thus, what is needed is a power-on reset circuit which is insensitive to transistor threshold voltage variations and consumes substantially zero power in steady state.